Topological Materials Could Shrink Chip Interconnects and replace copper

Amazing stuff!

"... However, as electronics continue to shrink, copper becomes a dramatically worse conductor. Now scientists find that a new class of materials containing exotic quasiparticles might one day help enable next-generation interconnects that become better conductors the thinner they get. ...

Once copper wires shrink beneath this limit—in copper’s case, 40 nanometers—their electrical conductivity drops dramatically because their electrons start experiencing more collisions. ...

Researchers are investigating other metals that show better conductivity at nanometer scales for use in interconnects. For instance, cobalt and ruthenium have electron mean free paths of 10 nm and 6 nm, respectively. This means interconnects made from these metals can get smaller than copper wires before running into the same conductivity problem. However, if they shrink far enough, they will have to deal with the same challenge. ...

In a new study, scientists instead investigated topological materials, which possess extraordinary properties based on the topology of their structures. The researchers synthesized nanowires made of one such material as a proof of concept. ...

In the new study, ... synthesized nanowires of the Weyl semimetal niobium arsenide using a method known as thermomechanical nanomolding. This method allowed the researchers to make a single-crystal nanowire 2 to 3 micrometers long and as thin as 40 nm.

The scientists found the resistivity of niobium arsenide nanowires dropped with decreasing diameter. At room temperature, a 40-nm-wide nanowire displayed a resistivity about 70 percent lower than that of bulk single crystals. Their analyses suggest this improvement was due to surface conduction. ..."

From the editor's summary and abstract:

"Editor’s summary

Nanowires of the topological Weyl semimetal niobium arsenide (NbAs) are three to four times as conductive as the bulk material. Cheon et al. used thermomechanical nanomolding to grow single-crystalline nanowires with diameters as small as 40 nanometers. These stable nanowires also have favorable breakdown current density and thermal conductivity that could enable application as interconnects in electronics. ...

Abstract

Ongoing demands for smaller and more energy-efficient electronic devices necessitate alternative interconnect materials with lower electrical resistivity at reduced dimensions.

We report the synthesis of Weyl semimetal niobium arsenide (NbAs) nanowires through thermomechanical nanomolding with single crystallinity and controlled diameters down to 40 nanometers.

The resistivity of NbAs nanowires decreases with decreasing diameter, and 40-nanometer-diameter nanowires exhibited a room-temperature resistivity of 10.5 ± 1.9 microhm·centimeters, which is ~70% lower than their bulk counterpart.

Calculations attribute this resistivity reduction to surface-dominant conduction with a long carrier lifetime at finite temperatures. Further characterization of nanowires and bulk crystals revealed high breakdown current density, stability, and thermal conductivity.

These properties highlight the potential of NbAs nanowires as next-generation interconnects that could surpass the limitations of current copper-based interconnects."

Topological Materials Could Shrink Chip Interconnects - IEEE Spectrum "New materials grow more conductive as they get smaller, not less"

Surface-dominant transport in Weyl semimetal NbAs nanowires for next-generation interconnects (no public access)

Surface-dominant transport in Weyl semimetal NbAs nanowires for next-generation interconnects (preprint, open access)

The nanowires seen in this electron microscope image were molded from a bulk feedstock of niobium arsenide crystals.

Anthropic is hiring an AI chip design team following in the footsteps of e.g. Google, OpenAI and Meta

Google did something similar about 2015 when it introduced it's TPU processor.

Alea iacta est! (The chips [dies] is cast! Famous quote by Cesar in 49 BC/BCE before crossing the Rubicon river. Pardon my pun!

"A Google Tensor Processing Unit (TPU) is a custom application-specific integrated circuit (ASIC) designed specifically to accelerate machine learning and artificial intelligence workloads. First deployed internally in 2015, TPUs power major Google services like Search, YouTube, and Gemini" (Google Search)

"... Anthropic isn’t the first AI company to decide to build its own chip.

In June, OpenAI unveiled its Broadcom-built Jalapeño chip, which is designed specifically for inference workloads.

Google DeepMind has long relied on Alphabet’s TPU chips to power its AI models, while 

Meta has been developing its own MTIA accelerators for AI workloads. ..."

Anthropic is hiring an AI chip design team | TechCrunch "Anthropic is building a team to design its own custom chips for AI usage."

Taiwan alleges ex-TSMC staff stole chip secrets to sell to China

Bad news! Sounds familiar!

"Taiwanese prosecutors on Monday indicted a former TSMC deputy manager for allegedly stealing trade secrets involving national core technologies with the intent of using them to advance China's chip ambitions. ..."

Taiwan alleges ex-TSMC staff stole chip secrets to sell to China - Nikkei Asia "Indictment is first under National Security Act involving attempt to advance Chinese chip ambitions"

What is IBM’s nanostack chip architecture? - IBM Research

Recommendable! Explains the latest chip design breakthrough by Big Blue!

See also my recent blog post here regarding new IBM chips.

What is IBM’s nanostack chip architecture? - IBM Research "This new microchip architecture from IBM builds up, not out, to overcome the spatial limitations of scaling transistor density."

Nanosheet transistor architecture (center), introduced by IBM in 2017, has supplanted the previously dominant FinFET technology (left). Nanostack transistor architecture (right) is expected to extend transistor scaling for more than a decade.

IBM makes chip design breakthrough with 3D architecture, would reach AI chips by 2030

Good news! Good old big blue is alive and kicking! From mainframes to AI!

"IBM announced the first sub-1 nanometer chip technology, with transistor nodes measuring just 0.7 nanometers wide. The breakthrough allows designers to cram nearly 100 billion transistors into a fingernail-sized chip, about 10,000 times denser than a red blood cell is wide.

Performance jumps are substantial: The chips deliver 70 percent better efficiency or 50 percent more power than IBM’s previous 2nm designs, and researchers estimate AI accelerators built with the technology could hit 9,000 TOPS, six times today’s leading hardware.

The advance relies on what IBM calls “nanostack” architecture, which stacks transistors vertically rather than just shrinking them in two dimensions, along with breakthroughs in wafer bonding and a 40 percent increase in on-chip SRAM capacity. IBM expects the nanostack design to anchor at least a decade of silicon innovation, though widespread adoption is still years away. (IBM)"

"... IBM announced it's once again unveiling the smallest, most powerful computer chip technology in the world. These are the first sub-1 nanometer node chips, designed with transistor nodes that are just 0.7 nanometers, or 7 angstroms, wide. That makes them the smallest transistors in the world — by some margin. ..."

Data Points: GPT-5.6 arrives, but only for approved partners

https://research.ibm.com/blog/sub-1nm-node-chips "It’s the world’s first 0.7nm chip technology. Powered by IBM’s new nanostack architecture, this structure will pave the way for more powerful and efficient chips for years to come. This is the architecture to accelerate the Angstrom era."

AI agent autonomously designs functional RISC-V CPU chip in 12 hours

Good news! This is only the beginning!

 
"AI autonomously designs functional CPU chip

 An agentic AI system autonomously designed a 1.48 gigahertz RISC-V CPU chip, roughly equivalent to a 2011-vintage Intel Celeron SU2300, from a 219-word specification, according to a paper by researchers at the AI chip design startup Verkor.

The resulting design has not been physically fabricated, but the authors verified it in simulation. The system took 12 hours to generate the design, in contrast to the typical timeline of 18 to 36 months. However, it consumed tens of billions of tokens and a team of up to 10 human experts likely would be required to implement the design. For AI developers, this demonstrates the potential for agentic workflows to compress hardware development timelines from months to hours, though significant hurdles remain." (Datapoints)

"AI chip design startup Verkor.io claims, in a research paper published in March, that its agentic AI system, Design Conductor, autonomously produced a complete RISC-V CPU core — taking a 219-word requirements document and generating a verified, layout-ready design in 12 hours, which is orders of magnitude faster than the standard 18- to 36-month timelines seen in commercial chip design. ..."

From the abstract:

"Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file).

In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document.

The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII.  ..."

AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens'

Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU (preprint, open access)

TU München baut ersten europaweiten KI-Chip mit moderner 7-Nanometer-Technologie

Na was für eine positive Überraschung!

"... Der KI-Chip basiert auf dem Open-Source-Standard Risc-V. So entstehen für die TUM keine Lizenzkosten. Außerdem ist ein solcher offener Standard deutlich transparenter und man kann nachvollziehen, wie der Kern eines solches Chips aufgebaut ist. ..."

TU München baut ersten europaweiten KI-Chip mit moderner 7-Nanometer-Technologie "An der Technischen Universität München (TUM) ist der EU-weit erste KI-Chip mit moderner 7-Nanometer-Technologie entstanden. Ab 2028 sollen die Chips in Dresden gefertigt werden."

TUM baut eigenen KI-Chip in 7-nm-Technologie (original Mitteilung) "An der Technischen Universität München (TUM) ist der EU-weit erste KI-Chip mit moderner 7-Nanometer-Technologie entstanden. Prof. Hussam Amrouch entwickelte den neuromorphen Chip auf Grundlage des Standards des weltweit führenden Chip-Produzenten TSMC. Künftig will der Professor für KI-Prozessor-Design zusammen mit seiner Forschungsgruppe jährlich mindestens drei neue Designs entwerfen, die ab 2028 von der European Semiconductor Manufacturing Company (ESMC) in Dresden gefertigt werden sollen."

Das Foto ist vom 19.5.2025 (Quelle)

National Review: Trump’s China Chip Deal & Sale of American National Security. Really!

This article is the editor's pick for today of the National Review!

Well, the chips (H200 AI chip) now allowed to be sold to China are not the latest and best chips ((H100/H200, B200 GPU)!

Trump’s China Chip Deal & Sale of American National Security | National Review "If letting China buy precious tech is detrimental to U.S. interests, that threat is not mitigated by allowing the Treasury to grab a quarter of the income."

Diamond Thermal Conductivity: A New Era in Chip Cooling

Amazing stuff! Diamonds are a chip's best friend!

"When you grow a micrometers-thick layer of diamond inside advanced chips, it spreads out the heat and drops the temperature more than 50°C."

"... But with great power comes great…heat! ...

In some ways, diamond is ideal. It’s one of the most thermally conductive materials on the planet—many times more efficient than copper—yet it’s also electrically insulating. However, integrating it into chips is tricky: Until recently we knew how to grow it only at circuit-slagging temperatures in excess of 1,000 °C.

But my research group at Stanford University has managed what seemed impossible. We can now grow a form of diamond suitable for spreading heat, directly atop semiconductor devices at low enough temperatures that even the most delicate interconnects inside advanced chips will survive. To be clear, this isn’t the kind of diamond you see in jewelry, which is a large single crystal. Our diamonds are a polycrystalline coating no more than a couple of micrometers thick."

Diamond Thermal Conductivity: A New Era in Chip Cooling - IEEE Spectrum "A micrometers-thick integrated layer spreads out the heat"

Gallium nitride high-electron-mobility transistors were an ideal test case for diamond cooling. The devices are 3D and the critical heat-generating part, the two-dimensional electron gas, is close to the surface.

Polycrystalline diamond could help reduce temperatures inside 3D chips. Diamond thermal vias would grow inside micrometers-deep holes so heat can flow from vertically from one chip to a diamond heat spreader in another chip that’s stacked atop it.

New photonic chip boosts AI efficiency with light to cut energy use

Good news!

"... To tackle the growing energy demands of AI, researchers ... have built something dazzling. Their new chip, called a photonic joint transform correlator (pJTC), swaps electricity for light to handle one of AI's most power-hungry jobs. ..."

"... The prototype chip uses two sets of miniature Fresnel lenses using standard manufacturing processes. These two-dimensional versions of the same lenses found in lighthouses are just a fraction of the width of a human hair. Machine learning data, such as from an image or other pattern-recognition tasks, are converted into laser light on-chip and passed through the lenses. The results are then converted back into a digital signal to complete the AI task.

This lens-based convolution system is not only more computationally efficient, but it also reduces the computing time. Using light instead of electricity has other benefits, too. Sorger’s group designed a chip that could use different colored lasers to process multiple data streams in parallel. ..."

From the abstract:

"Convolutional operations are computationally intensive in artificial intelligence services, and their overhead in electronic hardware limits machine learning scaling. Here, we introduce a photonic joint transform correlator (pJTC) using a near-energy-free on-chip Fourier transformation to accelerate convolution operations. The pJTC reduces computational complexity for both convolution and cross-correlation from O(N4) to O(N2), where N2 is the input data size.

Demonstrating functional Fourier transforms and convolution, this pJTC achieves 98.0% accuracy on an exemplary MNIST inference task.

Furthermore, a wavelength-multiplexed pJTC architecture shows potential for high throughput and energy efficiency, reaching 305 TOPS/W and 40.2 TOPS/mm2, based on currently available foundry processes.

An efficient, compact, and low-latency convolution accelerator promises to advance next-generation AI capabilities across edge demands, high-performance computing, and cloud services."

New photonic chip boosts AI efficiency with light

New light-based chip boosts power efficiency of AI tasks 100 fold (original news release)

New light-based chip boosts power efficiency of AI tasks 100 fold (original news release)

Near-energy-free Photonic Fourier Transformation for Convolution Operation Acceler (preprint, open access)

pJTC Convolutional techniques.

(a) Comparison of spatial convolution, Fourier electrical convolution, and Fourier optical convolution in terms of computational complexity.

(b) Schematic of a JTC, demonstrating how it performs Fourier optical convolution by optically generating the Fourier transform of the combined input Signal and Kernel, detecting the intensity pattern, and producing the auto- and cross-correlation between Signal and Kernel.

(c) Optical microscope image of the fabricated SiPh chiplet from AIM Photonics. (d) Comparison of the initial MNIST image (green line), the output after an ideal Fourier transform (blue line), the output after the actual on-chip lens Fourier transform (yellow line), and the calibrated output obtained from the actual on-chip lens after applying phase correction (pink line). (e) Confusion matrix shows the classification accuracy for 10,000 test MNIST images with 10 percent random temporal delay introduced in the input electrical signal, achieving total accuracy of 95.3 percent.

Major energy savings with new memory chip breakthrough

Good news!

"... Now, researchers have developed layered material that can reduce the energy consumed by memory devices by a factor of 10 by doing away with the need for power-hungry external magnetic fields.

The alloy is made from the magnetic elements cobalt and iron, and nonmagnetic elements germanium and tellurium. It allows 2 opposing magnetic forces to coexist in the same thin material.

Until now, this has only been possible by stacking different ‘ferromagnetic’ and ‘antiferromagnetic’ materials in multilayer structures. ..."

"... To store information, memory devices must switch the direction of electrons within a material. With conventional materials, this typically requires an external magnetic field to alternate the electron orientation. ... new material, however, features a built-in combination of opposing magnetic forces that create an internal force and tilted overall magnetic alignment.

“This tilt allows electrons to switch direction rapidly and easily without the need for any external magnetic fields. By eliminating the need for power-hungry external magnetic fields, power consumption can be reduced by a factor of ten,” ..."

From the abstract:

"The discovery of van der Waals (vdW) magnetic materials exhibiting non-trivial and tunable magnetic interactions can lead to exotic magnetic states that are not readily attainable with conventional materials.

Such vdW magnets can provide a unique platform for studying new magnetic phenomena and realizing magnetization dynamics for energy-efficient and non-volatile spintronic memory and computing technologies.

Here, the coexistence of ferromagnetic and antiferromagnetic orders in vdW magnet (Co0.5Fe0.5)5-xGeTe2 (CFGT) above room temperature, inducing an intrinsic exchange bias and canted perpendicular magnetism is discovered.

Such non-trivial intrinsic magnetic order enables to realize energy-efficient, magnetic field-free, and deterministic spin-orbit torque (SOT) switching of CFGT in heterostructure with Pt.

These experiments, in conjunction with density functional theory and Monte Carlo simulations, demonstrate the coexistence of non-trivial magnetic orders in CFGT, which enables field-free SOT magnetization dynamics in spintronic devices."

Major energy savings with new memory chip breakthrough

Material breakthrough paves way for major energy savings in memory chips (original news release) "It is anticipated that, within just a few decades, the surging volume of digital data will constitute one of the world’s largest energy consumers. Now, researchers ... have made a breakthrough that could shift the paradigm: an atomically thin material that enables two opposing magnetic forces to coexist – dramatically reducing energy consumption in memory devices by a factor of ten. This discovery could pave the way for a new generation of ultra-efficient, reliable memory solutions for AI, mobile technology and advanced data processing."

Coexisting Non-Trivial Van der Waals Magnetic Orders Enable Field-Free Spin-Orbit Torque Magnetization Dynamics (open access)

Figure 1

Coexistence of ferro- and antiferro-magnetic orders in a single atomic stacking nanolayers of (Co0.5Fe0.5)5-xGeTe2. 

Low-power 'microwave brain' on a chip computes on both ultrafast data and wireless signals

Amazing stuff!

"... researchers have developed a low-power microchip they call a "microwave brain," the first processor to compute on both ultrafast data signals and wireless communication signals by harnessing the physics of microwaves. ..."

the processor is the first true microwave neural network and is fully integrated on a silicon microchip. It performs real-time frequency domain computation for tasks like radio signal decoding, radar target tracking and digital data processing, all while consuming less than 200 milliwatts of power. ..."

From the abstract:

"The development of high-bandwidth applications, including multi-gigabit communication and radar imaging, demands faster processing. However, in the microwave regime, where frequencies exceed clock rates, sampling and computation become challenging.

Here we report an integrated microwave neural network for broadband computation and communication. Our microwave neural network operates across tens of gigahertz but is reprogrammed with slow megabits per second control bitstreams.

By exploiting strong nonlinearity in coupled microwave oscillations, it expresses its computation in a narrower spectrum, enabling easy read-out. The system searches bit sequences in multi-gigabits per second data and emulates digital functions without custom circuits. It accelerates radio-frequency machine learning by classifying encoding schemes and detecting frequency shifts to track flight trajectories from radar.

The microwave neural network is fabricated with standard complementary metal–oxide–semiconductor technology. It occupies a sub-wavelength footprint of 0.088 mm2 on chip and has a sub-200-mW power consumption, supporting integration in a general-purpose analogue processor."

Low-power 'microwave brain' on a chip computes on both ultrafast data and wireless signals

An integrated microwave neural network for broadband computation and communication (no public access)

An integrated microwave neural network for broadband computation and communication (preprint, open access)

New transmitter chip could make wireless devices more energy-efficient

Good news!

"Researchers from MIT and elsewhere have designed a novel transmitter chip that significantly improves the energy efficiency of wireless communications, which could boost the range and battery life of a connected device.

Their approach employs a unique modulation scheme to encode digital data into a wireless signal, which reduces the amount of error in the transmission and leads to more reliable communications.

The compact, flexible system could be incorporated into existing internet-of-things devices to provide immediate gains, while also meeting the more stringent efficiency requirements of future 6G technologies. ...

When the signals aren’t uniform in length, it can be harder for the receiver to distinguish between symbols and noise that squeezed into the transmission.

To overcome this problem, the MIT transmitter adds a small amount of padding, in the form of extra bits between symbols, so that every transmission is the same length.

This helps the receiver identify the beginning and end of each transmission, preventing misinterpretation of the message. However, the device enjoys the energy efficiency gains of using a non-uniform, optimal modulation scheme. ...

This approach works because of a technique the researchers previously developed known as GRAND, which is a universal decoding algorithm that crack any code by guessing the noise that affected the transmission.

Here, they employ a GRAND-inspired algorithm to adjust the length of the received transmission by guessing the extra bits that have been added. In this way, the receiver can effectively reconstruct the original message. ..."

From the abstract:

"A fully integrated bits-to-RF transmitter featuring deep power back-off (PBO) enhancements is demonstrated, incorporating a time-interleaved multi-subharmonic-switching digital power amplifier (DPA) and a harmonic-rejection digital-to-phase converter (DPC).

This architecture also employs a non-uniform Optimal Modulation (OM) constellation to enhance the transmission error rate.

The system implemented in 65 nm CMOS achieves 58.1% peak power-added efficiency (PAE) and 52% peak system efficiency (SE) with 22.7 dBm peak output power, using 2.6 and 1.3 V VDDs.

Dynamic measurements of a 64-point OM constellation achieved 23.1% PAE and 19.4% SE at 16.9 dBm average output power, while maintaining an EVM of –29.9 dB at 1.5 GHz carrier frequency.

Compared to standard QAM, the proposed OM scheme reduces the bit error rate (BER) by 2.4× and the symbol error rate (SER) by 4.5×, demonstrating its suitability for high-efficiency and reliable signal transmission."

New transmitter could make wireless devices more energy-efficient | MIT News | Massachusetts Institute of Technology "The flexible chip could boost the performance of current electronics and meet the more stringent efficiency requirements of future 6G technologies."

A Fully Integrated Optimal Modulation Bits-to-RF Digital Transmitter using Time-Interleaved Multi-Subharmonic-Switching DPA (no public access)

Harvard’s ultra-thin chip could revolutionize quantum computing

Good news!

"Researchers at Harvard have created a groundbreaking metasurface that can replace bulky and complex optical components used in quantum computing with a single, ultra-thin, nanostructured layer. This innovation could make quantum networks far more scalable, stable, and compact. By harnessing the power of graph theory, the team simplified the design of these quantum metasurfaces, enabling them to generate entangled photons and perform sophisticated quantum operations — all on a chip thinner than a human hair. It's a radical leap forward for room-temperature quantum technology and photonics.

Key takeaways

• New research shows that metasurfaces could be used as strong linear quantum optical networks
• This approach could eliminate the need for waveguides and other conventional optical components
• Graph theory is helpful for designing the functionalities of quantum optical networks into a single metasurface

..."

"... created specially designed metasurfaces — flat devices etched with nanoscale light-manipulating patterns —  to act as ultra-thin upgrades for quantum-optical chips and setups. ..."

From the abstract of the perspective:

"A photon—the smallest discrete unit (quantum) of light—is a fundamental concept in various technologies such as secure communication and quantum computing. Identical photons can “feel” each other’s presence on a beam splitter, an optical device that separates a beam of light into distinct paths.

This so-called quantum interference is a straightforward method for generating quantum entanglement, in which two or more photons are linked regardless of their distance.

Entangling photons that travel across multiple paths is one of the primary challenges in quantum technologies. Existing devices occupy immense space for a handful of photonic qubits (quantum bits analogous to classical bits). ...

Yousef et al. (1) report a metasurface—a planar array of structures with sizes smaller than the wavelength of light—that can manage photons on demand. This produces a special class of quantum states in a miniature optical device with micrometer dimensions."

From the editor's summary and abstract:

"Editor’s summary

The bunching and antibunching of interfering single photons is a fundamental quantum effect that underpins the development of optical-based quantum computing and communication. Extending this Hong-Ou-Mandel (HOM) effect to larger systems requires an increasing number of bulky optical components that would be practically infeasible. Yousef et al. report on the use of metasurfaces as a multiport HOM interferometer and related quantum correlation measurements ... They also introduce a graph-theoretic formalism that represents both metasurface-based quantum optics and the resulting nonclassical correlation landscape. Such graphs can be used for the design of scalable, low-decoherence quantum information infrastructures. ...

Abstract

Multiphoton interference and entanglement are fundamental to quantum information science, yet extending these effects to higher-dimensional systems remains challenging given the imperfections and complexity of scaling conventional linear-optical setups.

We present a generalized Hong-Ou-Mandel effect using metasurfaces and graph theory, achieving controlled multiphoton bunching, antibunching, and entanglement across parallel Jones matrix–encoded spatial modes—all within a single-layer metasurface.

A graph-theoretic dual framework is introduced that simultaneously encodes the metasurface-based multiport interferometer designs and its resulting nonclassical correlations, enabling the direct translation of linear quantum optical networks into a single-layer metasurface.

We also demonstrate the ability of metasurfaces to produce multipath-entangled states and perform transformations equivalent to higher-order Hadamard interferometers. Our results underscore metasurface quantum graphs for scalable, low-decoherence quantum information infrastructure."

Harvard’s ultra-thin chip could revolutionize quantum computing | ScienceDaily "Researchers blend theoretical insight and precision experiments to entangle photons on an ultra-thin chip."

Researchers blend theoretical insight and precision experiments to entangle photons on an ultra-thin chip (original news release)

Flat optics produces quantum graphs (perspective, no public access) "A miniature device links multiple photon paths for bespoke entanglement"

Metasurface quantum graphs for generalized Hong-Ou-Mandel interference (no public access)

Schematic depiction of metasurface-based optical setup in the lab. 

Amazon’s Constellation of new data centers costing $100 billion this year alone

Good news (but aged)!

"Amazon revealed new details of its plan to build a constellation of massive data centers and connect them into an “ultracluster.” Customer Number One: Anthropic.

What’s new: Dubbed Project Rainier, the plan calls for Amazon to build seven next-generation data centers — with up to 30 on the drawing board — near New Carlisle, Indiana, ... Still other data centers will be located in Mississippi, and possibly in North Carolina and Pennsylvania, contributing to an expected $100 billion in capital expenditures this year alone. These plans complement the company’s previously announced intention to spend $11 billion worth on data centers in the United Kingdom by 2028. ...

The data centers will be based on Amazon-designed Trainium 2 and upcoming Trainium 3 processors, which are optimized to process large transformers, rather than processors from industry leader Nvidia or challenger AMD. Trainium 2 delivers lower performance but greater energy efficiency, and Trainium 3 will deliver 4 times greater performance while using 60 percent as much energy ...

using a network interface of its own design, Elastic Fabric Adapter, rather than interconnect technologies typically used by its competitors."

Amazon’s $100 Billion Bet, Meta’s Sensor-Packed Glasses, Anthropic’s Reason-Free Reasoning, Google’s Extreme Weather Prediction

Australian engineers at CSIRO use quantum machine learning for semiconductor fabrication in world first

Good news!

"Engineers at Australia’s national science agency, CSIRO, have performed a world-first use of quantum machine learning to fabricate semiconductors. The research could reshape the way future microchips are designed. ...

The team was particularly interested in modelling the Ohmic contact resistance of the semiconductor material. This property is a measure of the electrical resistance where the semiconductor comes into contact with a metal and the current flows easily between the materials in both directions.

Modelling Ohmic contact resistance is critical to semiconductor design and fabrication, but it’s also a property which is notoriously difficult to model. ...

The team developed an innovative Quantum Kernel-Aligned Regressor (QKAR) architecture.

Their QKAR setup included a Pauli-Z quantum feature map – a mathematical operator which can translate classical data into quantum states in the form of 5 quantum bits, or qubits.

Once data is mapped to the qubits, a quantum kernel alignment layer is used to perform the machine learning. ..."

From the abstract:

"Modeling complex semiconductor fabrication processes such as Ohmic contact formation remains challenging due to high-dimensional parameter spaces and limited experimental data.

While classical machine learning (CML) approaches have been successful in many domains, their performance degrades in small-sample, nonlinear scenarios.

In this work, quantum machine learning (QML) is investigated as an alternative, exploiting quantum kernels to capture intricate correlations from compact datasets. Using only 159 experimental GaN HEMT samples, a quantum kernel-aligned regressor (QKAR) is developed combining a shallow Pauli-Z feature map with a trainable quantum kernel alignment (QKA) layer.

All models, including seven baseline CML regressors, are evaluated under a unified PCA-based preprocessing pipeline to ensure a fair comparison. QKAR consistently outperforms classical baselines across multiple metrics (MAE, MSE, RMSE), achieving a mean absolute error of 0.338 Ω·mm when validated on experimental data.

Noise robustness and generalization are further assessed through cross-validation and new device fabrication.

These findings suggest that carefully constructed QML models can provide predictive advantages in data-constrained semiconductor modeling, offering a foundation for practical deployment on near-term quantum hardware. While challenges remain for both QML and CML, this study demonstrates QML's potential as a complementary approach in complex process modeling tasks."

Australian engineers at CSIRO use quantum AI for semiconductor fabrication in world first

Quantum Kernel Learning for Small Dataset Modeling in Semiconductor Fabrication: Application to Ohmic Contact

Fig. 7 The process of how to build the QML model.

TSMC’s 1.4nm Process: Each Wafer is estimated to Cost $45,000 planned to be released in 2028

Wow! Pocket change? 😊

"Established names in the technology industry, such as Apple, MediaTek, Qualcomm, and others, are already gunning for TSMC’s 2nm process, with the latter said to have started accepting orders from April 1. At $30,000 per wafer ... 

Unfortunately, it gets only harder from here, because a recent estimate claims that ... 1.4nm ‘Angstrom’ will serve as the immediate successor, but its cost may reach $45,000. ..."

TSMC’s 1.4nm Process, Also Called Angstrom, Will Make Even The Most Lucrative Clients Think Twice When Placing Orders, With An Estimate Claiming That Each Wafer Will Cost $45,000

Credits: Last Week in AI

2nm Wafer or is it gold: Very precious, don't drop it! 😊

The lab in Texas where Amazon Web Services designs custom chips

Amazon, a chipmaker? Can you have any of their chips home delivered?

"Annapurna Labs is a specialist microelectronics company Amazon acquired in 2015. Like its parent company, Annapurna Labs got its start in a household garage, and a lot has changed but the scrappy startup mentality remains. The lab’s specialist engineers, computer scientists, operations and logistics experts, and more—take a hands-on approach to every aspect of developing custom silicon chips and accelerators. No job is too small, even the ones requiring microscopic probes. ...

Annapurna Labs’ vertically integrated process enables control of the entire stack of components required for machine learning accelerator servers. Both software and hardware engineers collaborate at every stage of development, from chip design to server deployment in AWS data centers. ..."

Follow us into the lab where AWS designs custom chips "Annapurna Labs’ unique approach to innovation pushes the limits of computer software and hardware development."

Credits: Zu Besuch bei Amazons neuer Geheimwaffe

How Intel’s New CEO Can Catch Up to Samsung, Nvidia and TSMC

Recommendable! However, the title of this video is misleading. Oddly enough, the video does not mention smartphone chips at all!

AI unveils strange chip designs, while discovering new functionalities

Good news! What a great spiral of innovation! Progress at a breathtaking speed!

"... Now, researchers at Princeton Engineering and the Indian Institute of Technology have harnessed artificial intelligence to take a key step toward slashing the time and cost of designing new wireless chips and discovering new functionalities to meet expanding demands for better wireless speed and performance. ...

What used to take weeks of highly skilled work can now be accomplished in hours. ...

Moreover, the AI behind the new system has produced strange new designs featuring unusual patterns of circuitry. ... the designs were unintuitive and unlikely to be developed by a human mind. But they frequently offer marked improvements over even the best standard chips. ..."

From the abstract:

"Millimeter-wave and terahertz integrated circuits and chips are expected to serve as the backbone for future wireless networks and high resolution sensing. However, design of these integrated circuits and chips can be quite complex, requiring years of human expertise, careful tailoring of hand crafted circuit topologies and co-design with parameterized and pre-selected templates of electromagnetic structures. These structures (radiative and non-radiative, single-port and multi-ports) are subsequently optimized through ad-hoc methods and parameter sweeps. Such bottom-up approaches with pre-selected regular topologies also fundamentally limit the design space.

Here, we demonstrate a universal inverse design approach for arbitrary-shaped complex multi-port electromagnetic structures with designer radiative and scattering properties, co-designed with active circuits. To allow such universalization, we employ deep learning based models, and demonstrate synthesis with several examples of complex mm-Wave passive structures and end-to-end integrated mm-Wave broadband circuits. The presented inverse design methodology, that produces the designs in minutes, can be transformative in opening up a new, previously inaccessible design space."

AI unveils strange chip designs, while discovering new functionalities

AI slashes cost and time for chip design, but that is not all (original news release) "Specialized microchips that manage signals at the cutting edge of wireless technology are astounding works of miniaturization and engineering. They’re also difficult and expensive to design."

Deep-learning enabled generalized inverse design of multi-port radio-frequency and sub-terahertz passives and integrated circuits (open access)

Fig. 1: Deep learning enabled generalized inverse synthesis of high-frequency circuits.