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"Researchers from MIT and elsewhere have designed a novel transmitter chip that significantly improves the energy efficiency of wireless communications, which could boost the range and battery life of a connected device.
Their approach employs a unique modulation scheme to encode digital data into a wireless signal, which reduces the amount of error in the transmission and leads to more reliable communications.
The compact, flexible system could be incorporated into existing internet-of-things devices to provide immediate gains, while also meeting the more stringent efficiency requirements of future 6G technologies. ...
When the signals aren’t uniform in length, it can be harder for the receiver to distinguish between symbols and noise that squeezed into the transmission.
To overcome this problem, the MIT transmitter adds a small amount of padding, in the form of extra bits between symbols, so that every transmission is the same length.
This helps the receiver identify the beginning and end of each transmission, preventing misinterpretation of the message. However, the device enjoys the energy efficiency gains of using a non-uniform, optimal modulation scheme. ...
This approach works because of a technique the researchers previously developed known as GRAND, which is a universal decoding algorithm that crack any code by guessing the noise that affected the transmission.
Here, they employ a GRAND-inspired algorithm to adjust the length of the received transmission by guessing the extra bits that have been added. In this way, the receiver can effectively reconstruct the original message. ..."
From the abstract:
"A fully integrated bits-to-RF transmitter featuring deep power back-off (PBO) enhancements is demonstrated, incorporating a time-interleaved multi-subharmonic-switching digital power amplifier (DPA) and a harmonic-rejection digital-to-phase converter (DPC).
This architecture also employs a non-uniform Optimal Modulation (OM) constellation to enhance the transmission error rate.
The system implemented in 65 nm CMOS achieves 58.1% peak power-added efficiency (PAE) and 52% peak system efficiency (SE) with 22.7 dBm peak output power, using 2.6 and 1.3 V VDDs.
Dynamic measurements of a 64-point OM constellation achieved 23.1% PAE and 19.4% SE at 16.9 dBm average output power, while maintaining an EVM of –29.9 dB at 1.5 GHz carrier frequency.
Compared to standard QAM, the proposed OM scheme reduces the bit error rate (BER) by 2.4× and the symbol error rate (SER) by 4.5×, demonstrating its suitability for high-efficiency and reliable signal transmission."
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