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"... This method of changing the electrical resistance in computer memory devices, and allowing information processing and memory to exist in the same place, could lead to the development of computer memory devices with far greater density, higher performance and lower energy consumption. ...
One potential solution to the problem of inefficient computer memory is a new type of technology known as resistive switching memory. Conventional memory devices are capable of two states: one or zero. A functioning resistive switching memory device however, would be capable of a continuous range of states – computer memory devices based on this principle would be capable of far greater density and speed. ..."
One potential solution to the problem of inefficient computer memory is a new type of technology known as resistive switching memory. Conventional memory devices are capable of two states: one or zero. A functioning resistive switching memory device however, would be capable of a continuous range of states – computer memory devices based on this principle would be capable of far greater density and speed. ..."
From the abstract (written exclusively for subject matter experts):
"A design concept of phase-separated amorphous nanocomposite thin films is presented that realizes interfacial resistive switching (RS) in hafnium oxide–based devices. The films are formed by incorporating an average of 7% Ba into hafnium oxide during pulsed laser deposition at temperatures ≤400°C. The added Ba prevents the films from crystallizing and leads to ∼20-nm-thin films consisting of an amorphous HfOx host matrix interspersed with ∼2-nm-wide, ∼5-to-10-nm-pitch Ba-rich amorphous nanocolumns penetrating approximately two-thirds through the films. This restricts the RS to an interfacial Schottky-like energy barrier whose magnitude is tuned by ionic migration under an applied electric field. Resulting devices achieve stable cycle-to-cycle, device-to-device, and sample-to-sample reproducibility with a measured switching endurance of ≥104 cycles for a memory window ≥10 at switching voltages of ±2 V. Each device can be set to multiple intermediate resistance states, which enables synaptic spike-timing–dependent plasticity. The presented concept unlocks additional design variables for RS devices."
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