Good news! Anew category of computer chip!
"... First announced this summer at Intel’s Architecture Day, Mount Evans pairs up to four Xeon CPUs with packet processing technology developed by Barefoot Networks, a networking startup Intel acquired in 2019. The IPU also packs up to sixteen Arm Neoverse N1 cores running as fast as 3Ghz as well as I/O interfaces, caches, and three dual-mode LPDDR4 controllers with 102Gbps of memory bandwidth. ...
“This ASIC supports many existing use cases including vSwitch offload, firewalls, virtual routing,” and telemetry functions, while supporting up to 200 million packets per second and up to 16 million secure connections ... “The Mount Evans IPU emulates NVMe devices at very high input and output operations per second (IOPS) rates by leveraging and extending the Intel Optane NVMe controller. The same Intel infrastructure OS that runs on FPGA-based IPUs will run on Mount Evans as well. Additional technology innovations in the Mount Evans IPU are a next-generation reliable transport protocol, co-innovated with [Google] to solve the long-tail latency problem on lossy networks, and our advanced crypto and compression accelerators.” ..."
“This ASIC supports many existing use cases including vSwitch offload, firewalls, virtual routing,” and telemetry functions, while supporting up to 200 million packets per second and up to 16 million secure connections ... “The Mount Evans IPU emulates NVMe devices at very high input and output operations per second (IOPS) rates by leveraging and extending the Intel Optane NVMe controller. The same Intel infrastructure OS that runs on FPGA-based IPUs will run on Mount Evans as well. Additional technology innovations in the Mount Evans IPU are a next-generation reliable transport protocol, co-innovated with [Google] to solve the long-tail latency problem on lossy networks, and our advanced crypto and compression accelerators.” ..."
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